The invention relates to an integrated memory including two potential nodes at which a supply voltage is present, and memory cells each having a selection transistor and a storage capacitor. Such memories are generally known, for example, as DRAMS (Dynamic Random Access Memories).
In order to counteract dips in supply voltages of integrated circuits in the event of severe loads that occur suddenly or due to a momentary failure of voltage supplies, it is known to provide buffer capacitors for buffering the supply voltage. Those buffer capacitors are generally disposed in such a way that the entire supply voltage to be buffered is dropped across the buffer capacitor. It can happen that capacitor electrodes are not completely insulated from one another due to production faults or due to overvoltages that occur during operation. Therefore, a leakage or short-circuit current driven by the supply voltage flows through the capacitor. That can lead to a dip in the supply voltage. Such a defect can cause the entire integrated circuit to be rendered unusable.
The problem is further aggravated when the capacitance required for buffering is obtained by connecting numerous capacitors in parallel. A defect in just a single one of the capacitors then suffices to render the entire chip unusable due to the associated short circuit of the supply voltage.
In Patent Abstracts of Japan, Vol. 018, No. 073 (E-1503), Feb. 7, 1994, relating to JP 05-284 670 A, a buffer circuit for a battery supply of an IC is described, which has two RC series circuits connected in parallel.
It is accordingly an object of the invention to provide an integrated memory with a buffer circuit for a supply voltage, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and in which impairment of the integrated memory due to a defect occurring in the buffer circuit is avoided to the greatest possible extent.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory, comprising two potential nodes at which a supply voltage is present; memory cells each including a selection transistor and a storage capacitor; at least one series circuit disposed between the two potential nodes, the at least one series circuit each having at least one buffer capacitor and one associated transistor, the associated transistor effecting current limiting in the event of a defect in the at least one buffer capacitor; each of the at least one buffer capacitor and associated transistor having a mutual configuration and dimensions like the selection transistor and storage capacitor of one of the memory cells and having only an electrical connection differing from the selection transistor and storage capacitor.
The buffer circuit according to the invention has a series circuit formed by a high-value resistance element and a buffer capacitor and the supply voltage to be buffered is present across the series circuit. If there is a defect in the buffer capacitor, the total resistance of the buffer circuit results from the sum of the short-circuit resistance of the capacitor and the resistance of the resistance element. If the resistance of the resistance element is chosen to be sufficiently high, this prevents an excessively large current from flowing through the buffer circuit in the event of a defect. The resistance element is dimensioned in such a way that the leakage current occurring in the event of a defect in the capacitor is limited to a desired maximum value. Therefore, even when the buffer circuit can no longer perform its buffering function due to a defect in the capacitor, it is possible to maintain the supply voltage prior to the collapse, with the result that the integrated circuit can continue to be used.
By way of example, the high-value resistance element may be a non-reactive resistor or a transistor. The resistance of the resistance element can be variable through a control terminal. Such a resistance element may be realized e.g. by a transistor or a variable non-reactive resistor.
In accordance with another feature of the invention, in the last-mentioned case, the buffer circuit has a control circuit, which controls the resistance of the resistance element through its control terminal. This has the advantage of permitting its resistance to be adapted to specific desires or defects that occur in the capacitor.
In accordance with a further feature of the invention, the control circuit is a voltage regulator which controls the resistance of the resistance element in a manner dependent on the potential at the second potential node. In this case, in the event of a dip in the supply voltage due to a defect in the buffer capacitor, the resistance is increased in an expedient manner until the leakage current flowing through the series circuit no longer appreciably impairs the supply voltage.
In accordance with an added feature of the invention, the control circuit is a current regulator which controls the resistance of the resistance element in a manner dependent on the current flow through the series circuit. That effect corresponds to that of the embodiment outlined above. The advantage of both embodiments is that the buffer circuit reacts flexibly to defects which occur in its capacitor. It may be provided that the voltage or current regulator only increases the resistance of the resistance element when the potential at the second node has fallen by a minimum amount, or when the leakage current has reached a minimum intensity.
In accordance with an additional feature of the invention, the control circuit is an adjustable voltage source which, at its output, generates an output voltage that is adjustable through a control input, and the output is connected to the control terminal of the resistance element. The output voltage of the voltage source is adjustable either once or repeatedly. It can be chosen after or in the course of the process for producing the buffer circuit or the integrated circuit including it. That may be done in such a way that the resistance of the transistor is adapted to production-dictated influences which have been ascertained beforehand or to defects that have been ascertained in the buffer capacitor. In this way, it is possible to preclude production-dictated influences on the function of the buffer circuit and to compensate for defects that have been ascertained. The adjustable voltage source may be programmable, for example.
In accordance with a concomitant feature of the invention, the buffer circuit has at least two series circuits each having a buffer capacitor and a high-value resistance element, wherein all of these series circuits are connected in parallel with one another, and the supply voltage to be buffered is dropped across this parallel circuit. This development has the advantage that in the event of a defect affecting individual capacitors, the short-circuit current thereof is limited in each case by the resistance element associated with them. Thus, due to the resistance element, a low-resistance short circuit in parallel with the intact series circuits is not produced. Therefore, the action of the intact buffer capacitors remains unaffected by the failure of the defective buffer capacitors. The supply voltage is then buffered by the buffer capacitors which are still intact. If there is a large number of series circuits connected in parallel and only a few of them fail, the total capacitance of the parallel circuit is hardly reduced as compared with the case in which all of the capacitors are intact.
If the integrated memory circuit having a supply voltage which is intended to be buffered is an integrated memory circuit having memory cells each including a selection transistor and a storage capacitor (as is the case with DRAMs, for example), it is particularly advantageous to dimension the buffer circuit in exactly the same way as the memory cells, and the individual series circuits of the buffer circuit differ from the memory cells only by the way in which they are electrically connected. Since the memory cells of memory circuits are always configured in an optimized manner with respect to area, an area-optimized configuration of the buffer circuit is obtained in this way at no great cost. The buffer circuit can be produced with only minor changes by using the layout of the memory cells.
In the last-mentioned embodiment of the invention, the high-value resistance element is a correspondingly connected transistor. A non-reactive resistor, for example, may also be involved in other embodiments of the invention.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated memory with a buffer circuit, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.